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MAX15070A/MAX15070B
7A Sink, 3A Source,
12ns, SOT23 MOSFET Drivers
Applications Information
Supply Bypassing, Device
Grounding, and Placement
Ample supply bypassing and device grounding are
extremely important because when large external capac-
itive loads are driven, the peak current at the V+ pin can
approach 3A, while at the GND pin, the peak current can
approach 7A. V CC drops and ground shifts are forms of
negative feedback for inverters and, if excessive, can
cause multiple switching when the IN- input is used and
the input slew rate is low. The device driving the input
should be referenced to the ICs’ GND pin, especially
when the IN- input is used. Ground shifts due to insuffi-
cient device grounding can disturb other circuits sharing
the same AC ground return path. Any series inductance
in the V+, P_OUT, N_OUT, and/or GND paths can cause
oscillations due to the very high di/dt that results when
the ICs are switched with any capacitive load. A 1 F F
or larger value ceramic capacitor is recommended,
bypassing V+ to GND and placed as close as possible
to the pins. When driving very large loads (e.g., 10nF)
at minimum rise time, 10 F F or more of parallel storage
capacitance is recommended. A ground plane is highly
recommended to minimize ground return resistance and
series inductance. Care should be taken to place the
ICs as close as possible to the external MOSFET being
driven to further minimize board inductance and AC path
resistance.
Power Dissipation
Power dissipation of the ICs consists of three compo-
nents, caused by the quiescent current, capacitive
charge and discharge of internal nodes, and the output
current (either capacitive or resistive load). The sum of
these components must be kept below the maximum
power-dissipation limit of the package at the operating
temperature.
The quiescent current is 0.5mA typical. The current
required to charge and discharge the internal nodes
is frequency dependent (see the Typical Operating
Characteristics ).
For capacitive loads, the total power dissipation is
Layout Information
The ICs’ MOSFET drivers source and sink large currents
to create very fast rise and fall edges at the gate of the
switching MOSFET. The high di/dt can cause unaccept-
able ringing if the trace lengths and impedances are not
well controlled. The following PCB layout guidelines are
recommended when designing with the ICs:
? Place one or more 1 F F decoupling ceramic
capacitor(s) from V+ to GND as close as possible to
the IC. At least one storage capacitor of 10 F F (min)
should be located on the PCB with a low resistance
path to the V+ pin of the ICs. There are two AC cur-
rent loops formed between the IC and the gate of
the MOSFET being driven. The MOSFET looks like
a large capacitance from gate to source when the
gate is being pulled low. The active current loop is
from N_OUT of the ICs to the MOSFET gate to the
MOSFET source and to GND of the ICs. When the
gate of the MOSFET is being pulled high, the active
current loop is from P_OUT of the ICs to the MOSFET
gate to the MOSFET source to the GND terminal of
the decoupling capacitor to the V+ terminal of the
decoupling capacitor and to the V+ terminal of the
ICs. While the charging current loop is important, the
discharging current loop is critical. It is important to
minimize the physical distance and the impedance
in these AC current paths.
? In a multilayer PCB, the component surface layer sur-
rounding the ICs should consist of a GND plane con-
taining the discharging and charging current loops.
Chip Information
Process: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages . Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character,
but the drawing pertains to the package regardless of RoHS
status.
approximately:
P = C LOAD x (V+) 2 x FREQ
where C LOAD is the capacitive load, V+ is the supply
voltage, and FREQ is the switching frequency.
PACKAGE
TYPE
6 SOT23
PACKAGE
CODE
U6+1
OUTLINE
NO.
21-0058
LAND
PATTERN NO.
90-0175
8
Maxim Integrated
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